Series on RISC-V on the Baidu Edgeboard ZU3EG
I haven't been writing blog articles ever since August, 2018. Under the strong request from @jiegec, I decided to record various related aspects of my recent works on booting untethered, standard Linux/RISC-V on a ZynqMP board, forming a series of blog articles of which you can find links below. The list may be updated if new, related articles come in.
This article serves mostly as a catalog for the coming up articles. If you're interested in why the whole idea has come up, read the section that follows.
- Development System Setup - Edgeboard RISC-V Series
- Meet the Baidu Edgeboard ZU3EG - Edgeboard RISC-V Series
- RISC-V Hardware Design: System & Block Design - Edgeboard RISC-V Series
- RISC-V Hardware Design: Debug via BSCAN Chain - Edgeboard RISC-V Series
- RISC-V Software Design: Bootloader - Edgeboard RISC-V Series
- RISC-V Software Design: PS System - Edgeboard RISC-V Series
Note: this section has not undergone thorough fact checks and may suffer from fallacies in factual accuracy or lack references. It is laid out here only for informative purposes.
The idea of running RISC-V on a ZynqMP dates back to 2019, when a project from the lab I'm currently in required an experimental platform about accelerators coupling with RISC-V. The board we were holding at the time was a Xilinx ZCU102. There had been a flow adapted from the original work of RocketChip on a Zynq from UCB. Built around
fesvr, the FrontEnd SerVeR, that project implemented a tethered system of RISC-V tied to the ARM core in a Zynq system via AXI. We will not cover too much the details of a
fesvr system; briefly speaking, the RISC-V core uses DRAM from Zynq PS via AXI master port, and accepts external control via the UCB-specific, undocumented HTIF interface over an AXI slave. This enabled various applications from ISA simulation to Linux boot.
While the idea of
fesvr may be appealing to the academic society due to its simplicity and various features, the HTIF interface was never documented thoroughly, making it difficult to analyze and extend, let alone standardize. The Untethered lowRISC project has enabled the Rocket cores to boot untethered-ly via the use of a Berkeley Bootloader. However, with the standardization of Machine-mode behavior by the RISC-V SBI specification and the release of the reference OpenSBI implementation, as well as the upstreaming of the GNU toolchain, U-Boot/RISC-V, and Linux/RISC-V, it's now time to follow the trend and build a new flow that adopts the standard paradigms of development on RISC-V.